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                                                     Bustakt / Front Side Bus (FSB): 
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                                                     133 MHz / 266 MHz (Double Data Rate) 
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                                                     453-pin staggered organic Pin Grid Array 
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                                                     PoweNow! Clock Control    - Halt State    - Stop Grant States    - Sleep State    - Probe State    - FID_Change State System Management Mode 
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                                                     Kern-Spannung (min/normal): 
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                                                     Verlustleistung (min/normal): 
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                                                     3,0 Watt (Stop Grant C3/S1) / 6,0 Watt 
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                                                     Thermal Design Power (TDP): 
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                                                | 
                                                     AMD K7 QuantiSpeed Microarchitektur  - nine-issue, superscalar, fully-pipelined core 
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                                                     0,13 µm copper process CMOS (Complementary Metal Oxide Semiconductor) 
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                                                     Befehlssatzerweiterungen: 
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                                                     MMX, Extensions to MMX, 3DNow!, Extensions to 3DNow! und SSE (Streaming SIMD Extensions) 
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                                                     On-Chip integriert  - One superscalar, fully pipelined, out-of-order, three-way floating-point engine 
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                                                     128 KB Level1 Cache:
 
  256 KB Level2 Cache: 
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                                                     - 2-way set associative - 64 KB Befehlscache, parity protected - 64 KB Datencache, ECC protected - 16-way set associative - gemeinsamer write-back Befehls- und Datencache 
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                                                     System Controller (North Bridge) Peripheral Bus Controller (South Bridge) Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units Three independent integer pipelines Three address calculation pipelines Advanced two-level Translation Look-aside Buffer (TLB) 
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                                                     Multiple x86 instruction decoders Hardware data pre-fetching 
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                                                     Multiprozessorunterstützung: 
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                                                | 
                                                     Verwendung des Performance Rating 
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